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REV. A
ADM1027
3
Parameter
Min
Typ
Max
Unit
Test Conditions/Comment
OPEN-DRAIN SERIAL DATA BUS
OUTPUT (SDA)
Output Low Voltage, V
OL
0.4
V
I
OUT
 = 4.0 mA, V
CC
 = 3.3 V
High Level Output Current, I
OH
0.1
1
mA
V
OUT
 = V
CC
SMBUS DIGITAL INPUTS
(SCL, SDA)
Input High Voltage, V
IH
2.0
V
Input Low Voltage, V
IL
0.4
V
Hysteresis
500
mV
DIGITAL INPUT LOGIC LEVELS
(VID04)
Input High Voltage, V
IH
1.7
V
Input Low Voltage, V
IL
0.8
V
DIGITAL INPUT LOGIC LEVELS
(TACH INPUTS)
Input High Voltage, V
IH
2.0
V
5.5
V
Maximum Input Voltage
Input Low Voltage, V
IL
0.8
V
0.3
V
Minimum Input Voltage
Hysteresis
0.5
V p-p
DIGITAL INPUT CURRENT
Input High Current, I
IH
1
mA
V
IN
 = V
CC
Input Low Current, I
IL
1
mA
V
IN
 = 0
Input Capacitance, C
IN
5
pF
SERIAL BUS TIMING
Clock Frequency, f
SCLK
10
100
kHz
See Figure 1
Glitch Immunity, t
SW
50
ns
See Figure 1
Bus Free Time, t
BUF
4.7
ms
See Figure 1
Start Setup Time, t
SU;STA
4.7
ms
See Figure 1
Start Hold Time, t
HD;STA
4.0
ms
See Figure 1
SCL Low Time, t
LOW
4.7
ms
See Figure 1
SCL High Time, t
HIGH
4.0
50
ms
See Figure 1
SCL, SDA Rise Time, t
r
1000
ns
See Figure 1
SCL, SDA Fall Time, t
f
300
ms
See Figure 1
Data Setup Time, t
SU;DAT
250
ns
See Figure 1
Data Hold Time, t
HD;DAT
300
ns
See Figure 1
Detect Clock Low Timeout, t
TIMEOUT
15
35
ms
Can Be Optionally Disabled
NOTES
1
All voltages are measured with respect to GND, unless otherwise specified.
2
Typicals are at T
A
= 40rC and represent the most likely parametric norm.
3
Logic inputs will accept input high voltages up to V
MAX
 even when the device is operating down to V
MIN
.
4
Timing specifications are tested at logic levels of V
IL
= 0.8 V for a falling edge and V
IH
= 2.0 V for a rising edge.
Specifications subject to change without notice.
Rev. 3 | Page 3 of 56 | www.onsemi.com
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